Jagadeesh Vasudevamurthy is a professor at EECE Department of ITU. He is a full-time software engineer in the area of electronic design automation (EDA), He has worked in the area of EDA for the last 30 years. He has written software at Cadence, Synplicity (Now Synopsys), Mentor graphics and Xilinx.
Jagadeesh Vasudevamurthy received B.Eng. degree (Electronics and communication) with first class with distinction from National Institute of Engineering, Mysore, India, an M.Tech degree (Computer Engineering) from Indian Institute of Technology Kharagpur, India and a Ph.D. degree (Computer Engineering) from McGill University, Montreal, Canada. His Ph.D. thesis got IEEE transaction on CAD best paper of award and also published as The Best of ICCAD: 20 Years of Excellence in Computer-Aided Design. His Ph.D. thesis is used as a fundamental decomposition and factorization algorithms in all the commercial and academic logic synthesis systems.
Dr. Vasudevamurthy is a senior member of IEEE and a member of ACM. He has also worked as a director of Engineering at Synplicity and Mentor Graphics. His passion is to write code and teach. He has trained thousands of students in the area of data structures, algorithms, digital design, FPGA, C++, Java and Verilog for the last 10 years through University of Santa Cruz (UCSC) at Silicon Valley.